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FS6377-01/FS6377-01G Programmable 3-PLL Clock Generator IC
1.0 Features
* Three on-chip PLLs with programmable reference and feedback dividers * Four independently programmable muxes and post dividers * I2CTM-bus serial interface * Programmable power-down of all PLLs and output clock drivers
Data Sheet
* One PLL and two mux/post-divider combinations can be modified by SEL_CD input * Tristate outputs for board testing * 5V to 3.3V operation * Accepts 5MHz to 27MHz crystal resonators * Commercial (FS6377-01) and industrial (FS6377-01i) temperature ranges
2.0 Description
The FS6377 is a CMOS clock generator IC designed to minimize cost and component count in a variety of electronic systems. Three I2C-programmable phaselocked loops feeding four programmable muxes and post dividers provide a high degree of flexibility.
SDA SEL_CD PD VSS XIN XOUT OE VDD
1 2 3
16 15 14
SCL CLK_A VDD CLK_B CLK_C VSS CLK_D ADDR
FS6377
4 5 6 7 8
13 12 11 10 9
16-pin (0.150") SOIC
Figure 1: Pin Configuration
XIN XOUT
Reference Oscillator PLL A
Mux A
Post Divider A
CLK_A
PD
Power Down Control PLL B
Mux B
Post Divider B
CLK_B
SCL SDA ADDR
I2C-bus Interface PLL C Mux C Post Divider C CLK_C
SEL_CD Mux D Post Divider D CLK_D
OE
FS6377
Figure 2: Block Diagram
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FS6377-01/FS6377-01G Programmable 3-PLL Clock Generator IC
Table 1. Pin Descriptions Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Type DIuO DI P AI AO DI P DI P DO DO P DO DIu
u u u
Data Sheet
Name SDA SEL_CD PD VSS XIN XOUT OE VDD ADDR CLK_D VSS CLK_C CLK_B VDD CLK_A SCL
Description Serial interface data input/output Selects one of two PLL C, mux D/C and post divider C/D combinations Power-down input Ground Crystal oscillator input Crystal oscillator output Output enable input Power supply (5V to 3.3V) Address select D clock output Ground C clock output B clock output Power supply (5V to 3.3V) A clock output Serial interface clock input
U
DIu
DO
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI = Input With Internal Pull-Up; DID = Input With Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input, DO = Digital Output; P = Power/Ground; # = Active Low pin
3.0 Functional Block Description
3.1 Phase Locked Loops Each of the three on-chip phase-locked loops (PLLs) is a standard phase- and frequency-locked loop architecture that multiplies a reference frequency to a desired frequency by a ratio of integers. This frequency multiplication is exact. As shown in Figure 3, each PLL consists of a reference divider, a phase-frequency detector (PFD), a charge pump, an internal loop filter, a voltage-controlled oscillator (VCO), and a feedback divider. During operation, the reference frequency (fREF), generated by the on-board crystal oscillator, is first reduced by the reference divider. The divider value is called the "modulus," and is denoted as NR for the reference divider. The divided reference is then fed into the PFD. The PFD controls the frequency of the VCO (fVCO) through the charge pump and loop filter. The VCO provides a highspeed, low noise, continuously variable frequency clock source for the PLL. The output of the VCO is fed back to the PFD through the feedback divider (the modulus is denoted by NF) to close the loop.
REFDIV[7:0] CP LFTC
Loop Filter
fREF Reference Divider
(NR)
PhaseFrequency Detector fPD
UP
Charge Pump
DOWN FBKDIV[10:0]
Voltage Controlled Oscillator
fVCO
Feedback Divider (NF)
Figure 3: PLL Diagram
The PFD will drive the VCO up or down in frequency until the divided reference frequency and the divided VCO frquency appearing at the inputs of the PFD are equal. The input/output relationship between the reference frequency and the VCO frequency is:
fVCO = fREF
()
NF NR
.
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FS6377-01/FS6377-01G Programmable 3-PLL Clock Generator IC
3.1.1 Reference Divider The reference divider is designed for low phase jitter. The divider accepts the output of the reference oscillator and provides a divided-down frequency to the PFD. The reference divider is an 8-bit divider, and can be
Data Sheet
programmed for any modulus from 1 to 255 by programming the equivalent binary value. A divide-by-256 can also be achieved by programming the eight bits to 00h.
3.1.2 Feedback Divider The feedback divider is based on a dual-modulus prescaler technique. The technique allows the same granularity as a fully programmable feedback divider, while still allowing the programmable portion to operate at low speed. A high-speed pre-divider (also called a prescaler) is placed between the VCO and the programmable feedback divider because of the high speeds at which the VCO can operate. The dual-modulus technique insures reliable operation at any speed that the VCO can achieve and reduces the overall power consumption of the divider. For example, a fixed divide-by-eight could be used in the feedback divider. Unfortunately, a divide-by-eight would limit the effective modulus of the entire feedback divider to multiples of eight. This limitation would restrict the ability of the PLL to achieve a desired input-frequency-to-outputfrequency ratio without making both the reference and feedback divider values comparatively large. A large feedback modulus means that the divided VCO frequency is relatively low, requiring a wide loop bandwidth to permit the low frequencies. A narrow loop bandwidth tuned to high frequencies is essential to minimizing jitter; therefore, divider moduli should always be as small as possible. To understand the operation, refer to Figure 4. The Mcounter (with a modulus always equal to M) is cascaded with the dual-modulus prescaler. The A-counter controls the modulus of the prescaler. If the value programmed into the A-counter is A, the prescaler will be set to divide by N+1 for A prescaler outputs. Thereafter, the prescaler divides by N until the M-counter output resets the Acounter, and the cycle begins again. Note that N=8 and A and M are binary numbers. Suppose that the A-counter is programmed to zero. The modulus of the prescaler will always be fixed at N; and the entire modulus of the feedback divider becomes MxN. Next, suppose that the A-counter is programmed to a one. This causes the prescaler to switch to a divide-by-N+1 for its first divide cycle and then revert to a divide-by-N. In effect, the A-counter absorbs (or "swallows") one extra clock during the entire cycle of the feedback divider. The overall modulus is now seen to be equal to MxN+1. This example can be extended to show that the feedback divider modulus is equal to MxN+A, where AfVCO
Dual Modulus Prescaler
FBKDIV[2:0]
M Counter
fPD
FBKDIV[10:3]
A Counter
Figure 4: Feedback Divider
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FS6377-01/FS6377-01G Programmable 3-PLL Clock Generator IC
3.1.3 Feedback Divider Programming For proper operation of the feedback divider, the A-counter must be programmed only for values that are less than or equal to the M-counter. Therefore, not all divider moduli below 56 are available for use. The selection of divider values is listed in Table 2.
Data Sheet
Above a modulus of 56, the feedback divider can be programmed to any value up to 2047.
Table 2. Feedback Divider Modulus Under 56 M-Counter: FBKDIV[10:3] 000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 8 16 24 32 40 48 56 001 9 17 25 33 41 49 57 18 26 34 42 50 58 27 35 43 51 59 36 44 52 60 45 53 61 54 62 63 A-Counter: FBKDIV[2:0] 010 011 100 101 110 111
Feedback Divider Modulus
3.2 Post Divider Muxes As shown in Figure 2, an input mux in front of each post divider stage can select from any one of the PLL frequencies or the reference frequency. The frequency selection is done via the I2C-bus.
The input frequency on two of the four muxes (mux C and D in Figure 2) can be changed without reprogramming by a logic-level input on the SEL_CD pin.
3.3 Post Dividers The post divider performs several useful functions. First, it allows the VCO to be operated in a narrower range of speeds compared to the variety of output clock speeds that the device is required to generate. Second, it changes the basic PLL equation to
divider moduli respectively, and fCLK and fREF are the output and reference oscillator frequencies. The extra integer in the denominator permits more flexibility in the programming of the loop for many applications where frequencies must be achieved exactly. The modulus on two of the four post dividers muxes (post dividers C and D in Figure 2) can be altered without reprogramming by a logic level on the SEL_CD pin.
fCLK = fREF
( )( )
NF NR 1 NP
where NF, NR and NP are the feedback, reference and post
4.0 Device Operation
The FS6377 powers up with all internal registers cleared to zero, delivering the crystal frequency to all outputs. For operation to occur, the registers must be loaded in a mostsignificant-bit (MSB) to least-significant-bit (LSB) order. The register mapping of the FS6377 is shown in Table 3, and I2C-bus programming information is detailed in Section 5.0. Control of the reference, feedback and post dividers is detailed in Table 5. Selection of these dividers directly controls how fast the VCO will run. The maximum VCO speed is noted in Table 13.
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FS6377-01/FS6377-01G Programmable 3-PLL Clock Generator IC
4.1 SEL_CD Input The SEL_CD pin provides a way to alter the operation of PLL C, muxes C and D and post dividers C and D without having to reprogram the device. A logic-low on the SEL_CD pin selects the control bits with a "C1" or "D1" notation, per Table 3. A logic-high on the SEL_CD pin selects the control bits with "C2" or "D2" notation, per
Data Sheet
Table 3. Note that changing between two running frequencies using the SEL_CD pin may produce glitches in the output, especially if the post-divider(s) is/are altered.
4.2 Power-Down and Output Enable A logic-high on the PD pin powers down only those portions of the FS6377 which have their respective powerdown control bits enabled. Note that the PD pin has an internal pull-up. When a post divider is powered down, the associated output driver is forced low. When all PLLs and post 4.3 Oscillator Overdrive For applications where an external reference clock is provided (and the crystal oscillator is not required), the reference clock should be connected to XOUT and XIN should be left unconnected (float). For best results, make sure the reference clock signal is as jitter-free as possible, can drive a 40pF load with fast
dividers are powered down the crystal oscillator is also powered down. The XIN pin is forced low, and the XOUT pin is pulled high. A logic-low on the OE pin tristates all output clocks. Note that this pin has an internal pull-up.
rise and fall times and can swing rail-to-rail. If the reference clock is not a rail-to-rail signal, the reference must be AC coupled to XOUT through a 0.01mF or 0.1mF capacitor. A minimum 1V peak-to-peak signal is required to drive the internal differential oscillator buffer.
5.0 I2C-bus Control Interface
This device is a read/write slave device meeting all Philips I2C-bus specifications except a "general call." The bus has to be controlled by a master device that generates the serial clock SCL, controls bus access and generates the START and STOP conditions while the device works as a slave. Both master and slave can operate as a transmitter or receiver, but the master device 5.1 Bus Conditions Data transfer on the bus can only be initiated when the bus is not busy. During the data transfer, the data line (SDA) must remain stable whenever the clock line (SCL) is high. Changes in the data line while the clock line is high will be determines which mode is activated. A device that sends data onto the bus is defined as the transmitter, and a device receiving data as the receiver. I2C-bus logic levels noted herein are based on a percentage of the power supply (VDD). A logic-one corresponds to a nominal voltage of VDD, while a logic-zero corresponds to ground (VSS).
interpreted by the device as a START or STOP condition. The following bus conditions are defined by the I2C-bus protocol.
5.1.1 Not Busy Both the data (SDA) and clock (SCL) lines remain high to indicate the bus is not busy.
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FS6377-01/FS6377-01G Programmable 3-PLL Clock Generator IC
5.1.2 START Data Transfer A high to low transition of the SDA line while the SCL input is high indicates a START condition. All commands to the device must be preceded by a START condition.
Data Sheet
5.1.3 STOP Data Transfer A low to high transition of the SDA line while SCL is held high indicates a STOP condition. All commands to the device must be followed by a STOP condition.
5.1.4 Data Valid The state of the SDA line represents valid data if the SDA line is stable for the duration of the high period of the SCL line after a START condition occurs. The data on the SDA line must be changed only during the low period of the SCL signal. There is one clock pulse per data bit. Each data transfer is initiated by a START condition and 5.1.5 Acknowledge When addressed, the receiving device is required to generate an acknowledge after each byte is received. The master device must generate an extra clock pulse to coincide with the acknowledge bit. The acknowledging device must pull the SDA line low during the high period of the master acknowledge clock pulse. Setup and hold times must be taken into account.
terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is determined by the master device, and can continue indefinitely. However, data that is overwritten to the device after the first sixteen bytes will overflow into the first register, then the second, and so on, in a first-in, firstoverwritten fashion.
The master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been read (clocked) out of the slave. In this case, the slave must leave the SDA line high to enable the master to generate a STOP condition.
5.2 I2C-bus Operation All programmable registers can be accessed randomly or sequentially via this bi-directional two wire digital interface. The device accepts the following I2C-bus commands.
5.2.1 Slave Address After generating a START condition, the bus master broadcasts a seven-bit slave address followed by a R/W bit. The address of the device is:
A6 1 A5 0 A4 1 A3 1 A2 X A1 0 A0 0
where X is controlled by the logic level at the ADDR pin. The variable ADDR bit allows two different devices to exist on the same bus. Note that every device on an I2C-bus must have a unique address to avoid bus conflicts. The default address sets A2 to one via the pull-up on the ADDR pin.
5.2.2 Random Register Write Procedure Random write operations allow the master to directly write to any register. To initiate a write procedure, the R/W bit that is transmitted after the seven-bit device address is a logic-low. This indicates to the addressed slave device that
a register address will follow after the slave device acknowledges its device address. The register address is written into the slave's address pointer. Following an acknowledge by the slave, the master is allowed to write
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FS6377-01/FS6377-01G Programmable 3-PLL Clock Generator IC
eight bits of data into the addressed register. A final acknowledge is returned by the device, and the master generates a STOP condition.
Data Sheet
If either a STOP or a repeated START condition occurs during a register write, the data that has been transferred is ignored.
5.2.3 Random Register Read Procedure Random read operations allow the master to directly read from any register. To perform a read procedure, the R/W bit that is transmitted after the seven-bit address is a logiclow, as in the register write procedure. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is then written into the slave's address pointer.
Following an acknowledge by the slave, the master generates a repeated START condition. The repeated START terminates the write procedure, but not until after the slave's address pointer is set. The slave address is then resent, with the R/W bit set this time to a logic-high, indicating to the slave that data will be read. The slave will acknowledge the device address, and then transmits the eight-bit word. The master does not acknowledge the transfer but does generate a STOP condition.
5.2.4 Sequential Register Write Procedure Sequential write operations allow the master to write to each register in order. The register pointer is automatically incremented after each write. This procedure is more efficient than the random register write if several registers must be written. To initiate a write procedure, the R/W bit that is transmitted after the seven-bit device address is a logic-low. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is written into the slave's address pointer. Following an acknowledge by the
slave, the master is allowed to write up to sixteen bytes of data into the addressed register before the register address pointer overflows back to the beginning address. An acknowledge by the device between each byte of data must occur before the next data byte is sent. Registers are updated every time the device sends an acknowledge to the host. The register update does not wait for the STOP condition to occur. Registers are therefore updated at different times during a sequential register write.
5.2.5 Sequential Register Read Procedure Sequential read operations allow the master to read from each register in order. The register pointer is automatically incremented by one after each read. This procedure is more efficient than the random register read if several registers must be read. To perform a read procedure, the R/W bit that is transmitted after the seven-bit address is a logic-low, as in the register write procedure. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is then written into the slave's address pointer.
Following an acknowledge by the slave, the master generates a repeated START condition. The repeated START terminates the write procedure, but not until after the slave's address pointer is set. The slave address is then resent, with the R/W bit set this time to a logic-high, indicating to the slave that data will be read. The slave will acknowledge the device address, and then transmits all 16 bytes of data starting with the initial addressed register. The register address pointer will overflow if the initial register address is larger than zero. After the last byte of data, the master does not acknowledge the transfer but does generate a STOP condition.
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FS6377-01/FS6377-01G Programmable 3-PLL Clock Generator IC
Data Sheet
S
DEVICE ADDRESS
WA
REGISTER ADDRESS
A
DATA
AP
7-bit Receive Device Address START Command
Register Address Acknowledge WRITE Command From bus host to device
Data Acknowledge STOP Condition Acknowledge From device to bus host
Figure 5: Random Register Write Procedure
S
DEVICE ADDRESS
WA
REGISTER ADDRESS
AS
DEVICE ADDRESS
RA
DATA
AP
7-bit Receive Device Address START Command
Register Address Acknowledge WRITE Command From bus host to device
7-bit Receive Device Address Repeat START Acknowledge From device to bus host
Data Acknowledge READ Command STOP Condition NO Acknowledge
Figure 6: Random Register Read Procedure
S
DEVICE ADDRESS
WA
REGISTER ADDRESS
A
DATA
A
DATA
A
DATA
AP
7-bit Receive Device Address START Command
Register Address Acknowledge WRITE Command From bus host to device
Data Acknowledge
Data Acknowledge Acknowledge
Data Acknowledge STOP Command
From device to bus host
Figure 7: Sequential Register Write Procedure
S
DEVICE ADDRESS
WA
REGISTER ADDRESS
AS
DEVICE ADDRESS
RA
DATA
A
DATA
AP
7-bit Receive Device Address START Command
Register Address Acknowledge WRITE Command From bus host to device
7-bit Receive Device Address Repeat START Acknowledge From device to bus host
Data Acknowledge READ Command Acknowledge
Data NO Acknowledge STOP Command
Figure 8: Sequential Register Read Procedure
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FS6377-01/FS6377-01G Programmable 3-PLL Clock Generator IC
6.0 Programming Information
Table 3. Register Map ADDRESS BYTE 15 BYTE 14 BYTE 13 BYTE 12 BYTE 11 BYTE 10 BYTE 9 BYTE 8 BYTE 7 BYTE 6 BYTE 5 BYTE 4 BYTE 3 BYTE 2 BYTE 1 BYTE 0 (Note: All register bits are cleared to zero on power-up) MUX_A[1:0] PDPLL_A MUX_B[1:0] PDPLL_B MUX_C1[1:0] (selected via SEL_CD = 0) PDPLL_C BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 PDPOST_D BIT 2 PDPOST_C BIT 1 BIT 0
Data Sheet
MUX_D2[1:0] (selected via SEL_CD = 1)
MUX_C2[1:0] (selected via SEL_CD = 1)
PDPOST_B PDPOST_A
POST_D2[3:0] (selected via SEL_CD = 1) POST_D1[3:0] (selected via SEL_CD = 0) POST_B[3:0] MUX_D1[1:0] (selected via SEL_CD = 0) Reserved (0) LFTC_C2 (SEL_CD=1) CP_C2 (SEL_CD=1)
POST_C2[3:0] (selected via SEL_CD = 1) POST_C1[3:0] (selected via SEL_CD = 0) POST_A[3:0] FBKDIV_D2[10:8] M-Counter (selected via SEL_CD pin = 1) FBKDIV_C2[2:0] A-Counter (selected via SEL_CD pin = 1)
FBKDIV_C2[7:3] M-Counter (selected via SEL_CD pin = 1) REFDIV_C2[7:0] (selected via SEL_CD pin = 1) LFTC_C1 (SEL_CD=0) CP_C1 (SEL_CD=0)
FBKDIV_C1[10:8] M-Counter (selected via SEL_CD = 0) FBKDIV_C1[2:0] A-Counter (selected via SEL_CD = 1)
FBKDIV_C1[7:3] M-Counter (selected via SEL_CD = 0) REFDIV_C1[7:0] (selected via SEL_CD = 0)
LFTC_B
CP_B
FBKDIV_B[10:8] M-Counter FBKDIV_B[2:0] A-Counter
FBKDIV_B[7:3] M-Counter REFDIV_B[7:0] LFTC_A CP_A
FBKDIV_A[10:8] M-Counter FBKDIV_A[2:0] A-Counter
FBKDIV_A[7:3] M-Counter REFDIV_A[7:0]
6.1 Control Bit Assignment If any PLL control bit is altered during device operation, including those bits controlling the reference and feedback dividers, the output frequency will slew smoothly (in a glitch-free manner) to the new frequency. The slew rate is related to the programmed loop filter time constant.
However, any programming changes to any mux or post divider control bits will cause a glitch on an operating clock output.
6.1.1 Power Down All power-down functions are controlled by enable bits. The bits select which portions of the device to power-down when the PD input is asserted.
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FS6377-01/FS6377-01G Programmable 3-PLL Clock Generator IC
Table 4. Power-Down Bits Name PDPLL_A (Bit 21) PDPLL_B (Bit 45) PDPLL_C (Bit 69) Reserved (0) (Bit 69) PDPOSTA (Bit 120) PDPOSTB (Bit 121) PDPOSTC (Bit 122) PDPOSTD (Bit 123) Description Power-Down PLL A Bit = 0 Power on Bit = 1 Power off Power-Down PLL B Bit = 0 Power on Bit = 1 Power off Power-Down PLL C Bit = 0 Power on Bit = 1 Power off Set these reserved bits to zero (0) Power-Down Bit = 0 Bit = 1 Power-Down Bit = 0 Bit = 1 Power-Down Bit = 0 Bit = 1 Power-Down Bit = 0 Bit = 1 POST divider A Power on Power off POST divider B Power on Power off POST divider C Power on Power off POST divider D Power on Power off Table 5. Divider Control Bits Name REFDIV_A[7:0] (Bits 7-0) REFDIV_B[7:0] (Bits 31-24) REFDIV_C1[7:0] (Bits 55-48) REFDIV_C2[7:0] (Bits 79-72) Description Reference Divider A (NR) Reference Divider B (NR) Reference Divider C1 (NR) selected when the SEL-CD pin = 0 Reference Divider C2 (NR) selected when the SEL-CD pin = 1 Feedback Divider A (NF) FBKDIV_A[10:0] (Bits 18-8) FBKDIV_A[2:0] FBKDIV_A[10:3]
Data Sheet
A-Counter value M-Counter value
Feedback Divider B (NF) FBKDIV_B[10:0] (Bits 42-32) FBKDIV_B[2:0] FBKDIV_B[10:3] A-Counter value M-Counter value
Feedback Divider C1 (NF) selected when the SEL-CD pin = 0 FBKDIV_C1[10:0] (Bits 66-56) FBKDIV_C1[2:0] FBKDIV_C1[10:3] A-Counter value M-Counter value
Feedback DividerC2 (NF) selected when the SEL-CD pin = 1 FBKDIV_C2[10:0] (Bits 90-80) FBKDIV_C2[2:0] FBKDIV_C2[10:3] A-Counter value M-Counter value
Table 6. Divider Control Bits Name POST_A[3:0] (Bits 99-96) POST_B[3:0] (Bits 103-100) POST_C1[3:0] (Bits 107-104) POST_C2[3:0] (Bits 115-112) POST_D1[3:0] (Bits 111-108) POST_D2[3:0] (Bits 119-116) Description POST divider A (see Table 7) POST divider B (see Table 7) POST divider C1 (see Table 7) selected when the SEL_CD pin = 0 POST divider C2 (see Table 7) selected when the SEL_CD pin = 1 POST divider D1 (see Table 7) selected when the SEL_CD pin = 0 POST divider D2 (see Table 7) selected when the SEL_CD pin = 1
Table 7. Post Divider Modulus BIT [3] 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BIT [2] 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BIT [1] 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BIT [0] 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DIVIDE BY 1 2 3 4 5 6 8 9 10 12 15 16 18 20 25 50
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FS6377-01/FS6377-01G Programmable 3-PLL Clock Generator IC
Table 8. PLL Tuning Bits Name LFTC_A (Bit 20) LFTC_B (Bit 44) Description Loop Filter Time Constant A Bit = 0 Bit = 1 Bit = 0 Short time constant: 7ms Long time constant: 20ms Short time constant: 7ms MUX_A[1:0] (Bits 23-22) Table 9. Mux Select Bits Name Description MUX A Frequency Select Bit 23 0 0 1 1 Bit 47 0 MUX_B[1:0] (Bits 47-46) 0 1 1 Bit 22 0 1 0 1 Bit 46 0 1 0 1
Data Sheet
Loop Filter Time Constant B Long time constant: 20ms Bit = 1 Loop Filter Time Constant C1 selected when the SEL_CD pin = 0 Short time constant: 7ms Bit = 0 Bit = 1 Long time constant: 20ms Loop Filter Time Constant C2 selected when the SEL_CD pin = 1 LFTC_C2 (Bit 92) CP_A (Bit 19) CP_B (Bit 43) Bit = 0 Bit = 1 Charge Pump A Bit = 0 Bit = 1 Charge Pump B Bit = 0 Bit = 1 Current = 2mA Current = 10mA Current = 2mA Current = 10mA Short time constant: 7ms Long time constant: 20ms
Reference frequency PLL A frequency PLL B frequency PLL C frequency
MUX B Frequency Select Reference frequency PLL A frequency PLL B frequency PLL C frequency
LFTC_C1 (Bit 68)
MUX C1 Frequency Select selected when the SEL_CD pin = 0 Bit 71 0 MUX_C1[1:0] (Bits 71-70) 0 1 1 Bit 70 0 1 0 1 Reference frequency PLL A frequency PLL B frequency PLL C frequency
Charge Pump C1 selected when the SEL_CD pin = 0 CP_C1 (Bit 67) Bit = 0 Bit = 1 Current = 2mA Current = 10mA MUX_C2[1:0] (Bits 125-124)
MUX C2 Frequency Select selected when the SEL_CD pin = 1 Bit 125 0 0 1 1 Bit 124 0 1 0 1 Reference frequency PLL A frequency PLL B frequency PLL C frequency
Charge Pump C2 selected when the SEL_CD pin = 1 CP_C2 (Bit 91) Bit = 0 Bit = 1 Current = 2mA Current = 10mA
MUX D1 Frequency Select selected when the SEL_CD pin = 0 Bit 95 0 MUX_D1[1:0] (Bits 95-94) 0 1 1 Bit 94 0 1 0 1 Reference frequency PLL A frequency PLL B frequency PLL C frequency
MUX D2 Frequency Select selected when the SEL_CD pin = 1 Bit 127 0 MUX_D2[1:0] (Bits 127-126) 0 1 1 Bit 126 0 1 0 1 Reference frequency PLL A frequency PLL B frequency PLL C frequency
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FS6377-01/FS6377-01G Programmable 3-PLL Clock Generator IC
7.0 Electrical Specifications
Table 10. Absolute Maximum Ratings Parameter Supply Voltage, dc (VSS = ground) Input Voltage, dc Output Voltage, dc Input Clamp Current, dc (VI < 0 or VI > VDD) Output Clamp Current, dc (VI < 0 or VI > VDD) Storage Temperature Range (non-condensing) Ambient Temperature Range, Under Bias Junction Temperature Reflow Solder Profile Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7) 2 Symbol VDD V1 VO IIK IOK TS TA TJ Min. VSS-0.5 VSS-0.5 VSS-0.5 -50 -50 -65 -55 Max. 7 VDD+0.5 VDD+0.5 50 50 150 125 150 Units V V V mA mA C C C
Data Sheet
Per IPC/JEDEC J-STD-020B kV
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance, functionality and reliability.
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy electrostatic discharge.
Table 11. Operating Conditions Parameter Supply Voltage Ambient Operating Temperature Range Crystal Resonator Frequency Crystal Resonator Load Capacitance Serial Data Transfer Rate Output Driver Load Capacitance CL Symbol VDD TA fXIN CXL Parallel resonant, AT cut Standard mode 10 Conditions/Description 5V 10% 3.3V 10% Commercial Industrial Min. 4.5 3 0 -40 5 18 100 15 Typ. 5 3.3 Max. 5.5 3.6 70 85 27 Units V C MHz pF kb/s pF
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FS6377-01/FS6377-01G Programmable 3-PLL Clock Generator IC
Table 12. DC Electrical Specifications Parameter Overall Supply Current, Dynamic, With Loaded Outputs Supply Current, Static Symbol IDD Conditions/Description VDD = 5.5V, fCLK = 50MHz, CL = 15pF See Figure 10 for more information VDD = 5.5V, device powered down VDD = 5.5V VDD = 3.6V VDD = 5.5V VDD = 3.6V VDD = 5.5V VDD = 3.6V -1 VIL = 0V VDD = 5.5V VDD = 3.6V VDD = 5.5V VDD = 3.6V VDD = 5.5V VDD = 3.6V -1 VIL = 0V -20 -36 26 2.4 2.0 VSS-0.3 VSS-0.3 -1 -20 VDD = 5.5V VDD = 3.6V VDD = 5.5V VDD = 5.5V, oscillator powered down VDD = 5.5V
As seen by an external crystal connected to XIN and XOUT As seen by an external clock driver on XOUT; XIN unconnected
Data Sheet
Min.
Typ. 43 0.3
Max.
Units mA mA
IDDL Power-Down, Output Enable Pins (PD, OE) High-Level Input Voltage Low-Level Input Voltage Hysteresis Voltage High-Level Input Current Low-Level Input Current (pull-up) Serial Interface I/O (SCL, SDA) High-Level Input Voltage Low-Level Input Voltage Hysteresis Voltage High-Level Input Current Low-Level Input Current (pull-up) Low-Level Output Sink Current (SDA) VIH VIL Vhys IIH IIL VIH VIL Vhys IIH IIL
3.85 2.52 VSS-0.3 VSS-0.3 2.20 1.44
VDD+0.3 VDD+0.3 1.65 1.08
V V V
1 -36 -80 VDD+0.3 VDD+0.3 1.65 1.08 2.20 1.44 1 -80
mA mA
-20 3.85 2.52 VSS-0.3 VSS-0.3
V V V mA mA mA
IOL VOL = 0.4V, VDD = 5.5V Mode and Frequency Select Inputs (ADDR, SEL_CD) High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current (pull-up) Crystal Oscillator Feedback (XIN) Threshold Bias Voltage High-Level Input Current Low-Level Input Current Crystal Loading Capacitance* Input Loading Capacitance* Crystal Oscillator Drive (XOUT) High-Level Output Source Current Low-Level Output Sink Current IOH VDD = V(XIN) = 5.5V, VO = 0V VDD = 5.5V, V(XIN) = 0V, VO = 5.5V VO = 2.4V VO = 0.4V VO = 0.5VDD; output driving high VO = 0.5VDD; output driving low -10 VDD = 5.5V, VO = 0V; shorted for 30s, max. VDD = VO = 5.5V, shorted for 30s, max. 10 -10 VTH IIH IIL CL(xtal) CL(XIN) VIH VIL IIH IIL VDD = 5.5V VDD = 3.6V VDD = 5.5V VDD = 3.6V
VDD+0.3 VDD+0.3 0.8 0.8 1 -36 2.9 1.7 54 -80
V V mA mA
V mA 15 mA mA pF pF 30 -30 mA mA mA mA W 10 mA mA mA -75
5 -25 -54 18 36 21 -21 -125 23 29 27 -150 123
IOL Clock Outputs (CLK_A, CLK_B, CLK_C, CLK_D) High-Level Output Source Current Low-Level Output Sink Current Output Impedance Tristate Output Current Short Circuit Source Current* Short Circuit Sink Current* IOH IOL ZOH ZOL IZ ISCH ISCL
Unless otherwise stated, VDD = 5.0V 10%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. Min. and Max. characterization data are 3s from typical. Negative currents indicate current flows out of the device.
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FS6377-01/FS6377-01G Programmable 3-PLL Clock Generator IC
Voltage Low Drive Current (mA) Voltage High Drive Current (mA) (V) (V) Min. Typ. Max. Min. Typ. Max. 0 0.2 0.5 0.7 1 1.2 1.5 1.7 2 2.2 2.5 2.7 3 3.5 4 4.5 5 5.5 0 9 22 29 39 44 51 55 60 62 65 65 66 67 68 69 0 11 25 34 46 52 61 66 73 77 81 83 85 87 88 89 91 0 12 29 40 55 64 76 83 92 97 104 108 112 117 119 120 121 123 0 0.5 1 1.5 2 2.5 2.7 3 3.2 3.5 3.7 4 4.2 4.5 4.7 5 5.2 5.5 -87 -85 -83 -80 -74 -65 -61 -53 -48 -39 -32 -21 -13 0 -112 -110 -108 -104 -97 -88 -84 -77 -71 -62 -55 -44 -36 -24 -15 0 -150 -147 -144 -139 -121 -116 -108 -102 -92 -85 -74 -65 -52 -43 -28 -11 0
-200 Output Voltage (V) -150 Output Current (mA) 50 100
Data Sheet
150
-131
0 -50 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
-100
MIN TYP MAX
The data in this table represents nominal charaterization data only.
Figure 9: CLK_A, CLK_B, CLK_C, CLK_D Clock Outputs
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14
FS6377-01/FS6377-01G Programmable 3-PLL Clock Generator IC
Data Sheet
110 100 90 Dynamic Current (mA) 80 70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 Output Frequency (MHz)
All outputs off except output under test, CL = OpF All outputs off except output under test All outputs at 200MHz except output under test All outputs at 4MHz except output under test All outputs at the same frequency All outputs at the same frequency, CL = OpF
VDD = 5.0V; Reference Frequency = 27.00MHz; VCO Frequency = 200MHz, CL = 17pF except where noted
45 40 35 Dynamic Current (mA) 30 25 20 15 10 5 0 0 10 20 30 40 50 60 70 80 90 100 Output Frequency (MHz)
All outputs off except output under test All outputs off except output under test, CL = OpF All outputs at 100MHz except output under test All outputs at 2MHz except output under test All outputs at the same frequency
All outputs at the same frequency, CL = OpF
VDD = 3.3V; Reference Frequency = 27.00MHz; VCO Frequency = 100MHz, CL = 17pF except where noted
Figure 10: Dynamic Current vs. Output Frequency
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FS6377-01/FS6377-01G Programmable 3-PLL Clock Generator IC
Table 13. AC Timing Specifications Parameter Overall Output Frequency* VCO Frequency* VCO Gain* Loop Filter Time Constant* Rise Time* Fall Time* Tristate Enable Delay* Tristate Disable Delay* Clock Stabilization Time* Divider Modulus Feedback Divider Reference Divider Post Divider Duty Cycle* NF NR NP See also Table 8
Ratio of pulse width (as measured from rising edge to next falling edge at 2.5V) to one clock period On rising edges 500ms apart at 2.5V relative to an ideal clock, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPX=50, no other PLLs active
Data Sheet
Symbol
Conditions/Description
Clock (MHz)
Min.
Typ.
Max.
Units
fO fVCO AVCO
VDD = 5.5V VDD = 3.6V VDD = 5.5V VDD = 3.6V LFTC bit = 0 LFTC bit = 1 VO = 0.5V to 4.5V; CL = 15pF VO = 0.3V to 3.0V; CL = 15pF VO = 4.5V to 0.5V; CL = 15pF VO = 3.0V to 0.3V; CL = 15pF
0.8 0.8 40 40 400 7 20 1.9 1.6 1.8 1.5 1 1
150 100 230 170
MHz MHz MHz/V ms ns ns
tr tr tPZL, tPZH tPZL, tPZH tSTB
8 8 100 1
ns ns ms ms
Output active from power-up, via PD pin After last register is written See also Table 2 8 1 1 100 100 50 100 50 45
2047 255 50 55 45 ps 165 110 ps 390 %
Clock Outputs (PLL A clock via CLK_A pin)
Jitter, Long Term (sy(t))*
tj(LT)
On rising edges 500ms apart at 2.5V relative to an ideal clock, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPX=50, all other PLLs active (B=60MHz, C=40MHz, D=14.318MHz) From rising edge to the next rising edge at 2.5V, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPX=50, no other PLLs active From rising edge to the next rising edge at 2.5V, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPX=50, all other PLLs active (B=60MHz, C=40MHz, D=14.318MHz)
Jitter, Period (peak-peak)*
tj(DP)
Unless otherwise stated, VDD = 5.0V 10%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. Min. and Max. characterization data are 3s from typical.
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16
FS6377-01/FS6377-01G Programmable 3-PLL Clock Generator IC
Table 13. AC Timing Specifications, Continued Parameter Symbol Conditions/Description Clock (MHz) Min. Typ. Max.
Data Sheet
Units
Clock Outputs (PLL B clock via CLK_B pin) Duty Cycle*
Ratio of pulse width (as measured from rising edge to next falling edge at 2.5V) to one clock period On rising edges 500ms apart at 2.5V relative to an ideal clock, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, no other PLLs active On rising edges 500ms apart at 2.5V relative to an ideal clock, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, all other PLLs active (A=50MHz, C=40MHz, D=14.318MHz) From rising edge to the next rising edge at 2.5V, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, no other PLLs active From rising edge to the next rising edge at 2.5V, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, all other PLLs active (A=50MHz, C=40MHz, D=14.318MHz)
100 100 60 100 60
45 45
55
%
Jitter, Long Term (sy(t))*
tj(LT)
ps 75 120 ps 400
Jitter, Period (peak-peak)*
tj(DP)
Clock Outputs (PLL_C clock via CLK_C pin) Duty Cycle*
Ratio of pulse width (as measured from rising edge to next falling edge at 2.5V) to one clock period On rising edges 500ms apart at 2.5V relative to an ideal clock, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, no other PLLs active On rising edges 500ms apart at 2.5V relative to an ideal clock, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, all other PLLs active (A=50MHz, B=60MHz, D=14.318MHz) From rising edge to the next rising edge at 2.5V, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, no other PLLs active From rising edge to the next rising edge at 2.5V, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, all other PLLs active (A=50MHz, B=60MHz, D=14.318MHz)
100 100 40 100 40
45 45
55
%
Jitter, Long Term (sy(t))*
tj(LT)
ps 105 120 ps 440
Jitter, Period (peak-peak)*
tj(DP)
Clock Outputs (Crystal Oscillator via CLK_D pin) Duty Cycle*
Ratio of pulse width (as measured from rising edge to next falling edge at 2.5V) to one clock period On rising edges 500ms apart at 2.5V relative to an ideal clock, CL=15pF, fXIN=14.318MHz, no other PLLs active From rising edge to the next rising edge at 2.5V, CL=15pF, fXIN=14.318MHz, all other PLLs active (A=50MHz, B=60MHz, C=40MHz) From rising edge to the next rising edge at 2.5V, CL=15pF, fXIN=14.318MHz, no other PLLs active From rising edge to the next rising edge at 2.5V, CL=15pF, fXIN=14.318MHz, all other PLLs active (A=50MHz, B=60MHz, C=40MHz)
14.318 14.318 14.318 14.318 14.318
45 20
55
%
Jitter, Long Term (sy(t))*
tj(LT
ps 40 90 450 ps
Jitter, Period (peak-peak)*
tj(DP)
Unless otherwise stated, VDD = 5.0V 10%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. Min. and Max. characterization data are 3s from typical.
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FS6377-01/FS6377-01G Programmable 3-PLL Clock Generator IC
Table 14. Serial Interface Timing Specifications Parameter Clock Frequency Set-up Time, START (repeated) Hold Time, START Set-up Time, Data Input Hold Time, Data Input Output Data Valid From Clock Rise Time, Data and Clock Fall Time, Data and Clock High Time, Clock Low Time, Clock Set-up Time, STOP Symbol fSCL tsu:STA tnd:STA tsu:DAT thd:DAT tAA tR tF tHI tLO tsu:STO SDA SDA
Minimum delay to bridge undefined region of the falling edge of SCL to avoid unintended START or STOP
Data Sheet
Conditions/Description SCL
Standard Mode Min. 0 4.7 4.7 4.0 250 0 3.5 1000 300 4.0 4.7 4.0 Max. 100
Units kHz ms ms ms ns ms ms ns ns ms ms ms
Bus Free Time Between STOP and START tBUF
SDA, SCL SDA, SCL SCL SCL
Unless otherwise stated, all power supplies = 3.3V 5%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. Min. and Max. characterization data are 3s from typical.
~ ~
SCL
tsu:STA thd:STA tsu:STO
~ ~
SDA
~ ~
START
ADDRESS OR DATA VALID
DATA CAN CHANGE
STOP
Figure 11: Bus Timing Data
tF
tHI
tR
~ ~
SCL
tLO tsu:STA thd:STA thd:DAT
tsu:DAT
tsu:STO
~ ~
SDA IN
tAA tAA
tBUF
~ ~
SDA OUT
Figure 12: Data Transfer Sequence
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18
FS6377-01/FS6377-01G Programmable 3-PLL Clock Generator IC
8.0 Package Information - For Both `Green' and `Non-Green'
Table 15. 16-pin SOIC (0.150") Package Dimensions Dimensions Inches Min. A A1 A2 B C D E e H h L Q 0.061 0.004 0.055 0.013 0.0075 0.386 0.150 0.230 0.010 0.016 0 Max. 0.068 0.0098 0.061 0.019 0.0098 0.393 0.157 0.244 0.016 0.035 8 Millimeters Min. 1.55 0.102 1.40 0.33 0.191 9.80 3.81 5.84 0.25 0.41 0 Max. 1.73 0.249 1.55 0.49 0.249 9.98 3.99 6.20 0.41 0.89 8
Data Sheet
0.050 BSC
1.27 BSC
Table 16. 16-pin SOIC (0.150") Package Characteristics Parameter Thermal Impedance, Junction to Free-Air 16-pin 0.150" SOIC Lead Inductance, Self Lead Inductance, Mutual Lead Capacitance, Bulk Symbol QJA L11 L12 C11 Conditions/Description Air flow = 0 m/s Corner lead Center lead Any lead to any adjacent lead Any lead to VSS Typ. 110 4.0 3.0 0.4 0.5 Units C/W nH nH pF
9.0 Ordering Information
9.1 Device Ordering Codes
Ordering Code 11486-801 11486-912 11486-901 Device Number FS6377-01 FS6377-01G FS6377-01i Package Type 16-pin (0.150") SOIC (Small Outline Package) Operating Temperature Range 0C to 70C (Commercial) Shipping Configuration Tape-and-Reel Tape-and-Reel Tape-and-Reel
16-pin (0.150") SOIC 0C to 70C (Commercial) (Small Outline Package) 'Green' or lead-free packaging 16-pin (0.150") SOIC (Small Outline Package) -40C to 85C (Industrial)
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19
FS6377-01/FS6377-01G Programmable 3-PLL Clock Generator IC
10.0 Demonstration Software
Windows 3.1x/95/98-based software is available from AMI Semiconductor that illustrates the capabilities of the FS6377. The software can operate under Windows NT. Contact your local sales representative or the company directly for more information.
Data Sheet
10.1 Software Requirements * PC running MS Windows 3.1x or 95/98. Software runs on Windows NT in a calculation mode only. * 1.8MB available space on hard drive C
10.2 Software Installation Instructions At the appropriate disk drive prompt (A:\) unzip the compressed demo files to a directory of your choice. Run setup.exe to install the software.
10.3 Demo Program Operation Launch the fs6377.exe program. Note that the parallel port can not be accessed if your machine is running Windows NT. A warning message will appear stating: "This version of the demo program cannot communicate with the FS6377 hardware when running on a Windows NT operating system. Do you want to continue anyway, using just the calculation features of this program?" Clicking OK starts the program for calculation only. FS6377 demo hardware is no longer supported. The opening screen is shown in Figure 13.
Figure 13: Opening Screen
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FS6377-01/FS6377-01G Programmable 3-PLL Clock Generator IC
10.3.1 Example Programming Type a value for the crystal resonator frequency in MHz in the reference crystal box. This frequency provides the basis for all of the PLL calculations that follow. Next, click on the PLL A box. A pop-up screen similar to Figure 14 should appear. Type in a desired output clock frequency in MHz, set the operating voltage (3.3V or 5V) and the desired maximum output frequency error.
Data Sheet
and mux D are also affected by the logic level on the SEL_CD pin, as are the post dividers C and D.
Figure 15: Post Divider Menu
Figure 14: PLL Screen
Pressing calculate solutions generates several possible divider and VCO-speed combinations. For a 100MHz output, the VCO should ideally operate at a higher frequency, and the reference and feedback dividers should be as small as possible. In this example, highlight Solution #7. Notice the VCO operates at 200MHz with a post divider of two to obtain an optimal 50 percent duty cycle. Now choose which mux and post divider to use (that is, choose an output pin for the 100MHz output). Selecting A places the PostDiv value in Solution #7 into post divider A and switches mux A to take the output of PLL A. The PLL screen should disappear, and now the value in the PLL A box is the new VCO frequency chosen in Solution #7. Also note that mux A has been switched to PLL A and the post pivider A has the chosen 100MHz output displayed. Repeat the steps for PLL B. PLL C supports two different output frequencies depending on the setting of the SEL_CD pin. Both mux C
Click on PLL C1 to open the PLL screen. Set a desired frequency, however, now choose the post divider B as the output divider. Notice the post divider box has split in two (as shown in Figure 15). The post divider B box now shows that the divider is dependent on the setting of the SEL_CD pin for as long as mux B is the PLL C output. Clicking on post divider A reveals a pull-down menu provided to permit adjustment of the post divider value independently of the PLL screen. A typical menu is shown in Figure 15. The range of possible post divider values is also given in Table 7. The register settings are shown to the left in the screen shown in Figure 13. Clicking on a register location displays a screen shown in Figure 16. Individual bits can be poked, or the entire register value can be changed.
Figure 16: Register Screen
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(c) 2004 AMI Semiconductor, Inc. AMI Semiconductor makes no warranty for the use of its products, other than those expressly contained in the company's standard warranty contained in AMI Semiconductor's Terms and Conditions. The company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of AMI Semiconductor are granted by the company in connection with the sale of AMI Semiconductor products, expressly or by implication. I2C is a licensed trademark of Philips Electronics, N.V. AMI Semiconductor reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. GM

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